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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. dimmable ac mains led driver with pfc and primary side regulation isl1904 the isl1904 is a high-performance , critical conduction mode (crcm), flyback controller used for single-stage conversion of the ac mains to a constant current source with power factor correction (pfc). the controller regulates the output current by monitoring the primary side swit ching current so the feedback signal does not cross the isolat ion barrier. operation in crcm allows near zero-voltage quas i-resonant switching (zvs) for improved efficiency while maximizing magnetic core utilization. the isl1904 led driver provides all of the features required for high-performance dimmable led ballast designs and supports ac or dc input, isolated or non-isolated flyback and boost topologies. this advanced bicmos controller features all of the functions required to design low cost low parts count led driver. features ? excellent led current regulation over line, load, and temperature ? 0 - 100% dimming with leading-edge (triac) and trailing-edge dimmers ? power factor correction for up to 0.995 power factor and less than 20% harmonic content ? critical conduction mode (crcm) operation for quasi-resonant high efficiency performance ? supports universal ac mains input ? configurable for pwm or dc current dimming control of leds ? monitors fet switching current for load regulation ? supports isolated and non-isolated boost and flyback topologies ? closed loop soft-start for no overshoot ? offref feature to set dimming off-point to improve fixture performance matching ? -40c to +125c operation ? pb-free (rohs compliant) applications ? industrial and commercial led lighting ? retrofit led lamps with triac dimming ? universal ac mains input led retrofit lamps ? ac or dc input led ballasts figure 1a. typical application figure 1b. led current vs line voltage figure 1. typical application performance dimmer emi filter ac mains 8 13 3 dhc 6 7 deladj gnd vref iout out oc fb isl1904 vdd cs+ 5 14 1 4 12 ac 10 ramp 16 9 verr 700 750 800 850 550 600 650 180 190 200 210 220 230 240 250 260 270 line voltage (v rms ) 6leds 4leds led current (ma) 5leds september 20, 2012 fn8286.1
isl1904 2 fn8286.1 september 20, 2012 functional block diagram - isl1904 out pwm comparator pwm latch + - s r q q + - ramp ac crcm detector f max clamp 200mv + - master oscillator reference out duty cycle to voltage converter low pass filter + - - deladj + - triangle wave generator clk - + pwmout verr 600mv dimming pwm ea1 crcm oscillator/pwm/error amplifiers oc leading edge blanking fb1 quasi-zvs delay iout refinbuff primary oc clk f min clamp peak detecto r 1/5 ss/5 1/5 verr/5 pwm verr _ + + bias and reference generator gnd vdd uvlo + - vref otp shutdown 150
isl1904 3 fn8286.1 september 20, 2012 typical application - dimmable isolated flyback 9 10 11 12 13 14 15 16 1 2 4 3 5 6 7 8 isl1904 emi filter cs+ dhc offref pwmout vref out vdd oc ovp ac iout ramp gnd fb deladj verr ac mains dimmer
isl1904 4 fn8286.1 september 20, 2012 typical application - isolated flyback with pwm dimming 9 10 11 12 13 14 15 16 1 2 4 3 5 6 7 8 cs+ dhc offref pwmout vref out vdd oc ovp ac iout ramp gnd fb deladj verr emi filter ac mains dimmer isl1904
isl1904 5 fn8286.1 september 20, 2012 typical application - dimmable dc input boost converter 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15 16 cs+ dhc offref pwmout vref out vdd oc ovp ac iout ramp gnd fb deladj verr 9v to 26v pwm dimming input 90hz to 140hz, 0v to 4v 0 to 100% duty cycle isl1904
isl1904 6 fn8286.1 september 20, 2012 typical application - dimmable invertin g boost-buck (single winding flyback) 9 10 11 12 13 14 15 16 1 2 4 3 5 6 7 8 cs+ dhc offref pwmout vref out vdd oc ovp ac iout ramp gnd fb deladj verr emi filter ac mains dimmer isl1904
isl1904 7 fn8286.1 september 20, 2012 pin configuration isl1904 (16 ld qsop) top view cs+ dhc offref pwmout vref out vdd oc ovp 1 2 4 3 5 6 7 8 ac iout ramp 9 10 11 12 13 14 15 16 gnd fb deladj verr pin descriptions pin # symbol description 1 vdd vdd is the power connection for the ic. to optimize noise i mmunity, bypass vdd to gnd with a ceramic capacitor as close to the vdd and gnd pins as possible. 2 offref sets the reference level to disable the driver at light lo ading. the turn-off reference ca n be set at any level between 0 and 0.6v, corresponding to 0 to 100% of output loading. this feature is normally used in triac-based wall dimmer applications to disable the output before the dimmer becomes unstable due to insufficient holding current. 3 vref the 5.40v reference voltage output having 100 mv tolerance over line, load and operating temperature. bypass to gnd with a 0.1f to 3.3f low esr capacitor. 4 iout a pwm voltage signal with amplitude and duty cycle proporti onal to the peak switching current used to determine the output current. 5 cs+ the input for the crcm current sense circ uit. this input monitors the winding current to determine the critical conduction operating point. 6 oc the input to the load current sensing circuitry and the peak overcurrent comparator. the signal is sampled at the peak curre nt level for each switching cycle, amplified, and output on iout as a pw m signal. it must be scaled, filtered and averaged prior to bein g applied to the fb pin of the ea. the overcurrent comparator thre shold is set at 600mv nominal. pe ak ocp performs cycle-by-cycle over current protection. ocp includes leading-edge-blanking (leb), which blocks the signal at the beginning of the out pulse fo r the duration of the blanking period and when the out pulse is low. 7 fb fb is the inverting input to the error amplifier (ea). the fee dback signal from iout, after being scaled and filtered, is ap plied to the error amplifier. 8 deladj sets delay before a new switching cycles starts. this adju stment allows the user to delay the next switching cycle until the switching fet drain-source voltage reaches a minimum value to allow quasi-zvs (zero voltage switching) operation. a resistor to ground programs the delay. pulling deladj to vref disables the crcm oscillator. 9 verr output of the error amplifiers and the control voltage inpu t to the inverting input of the pwm comparator. verr cannot sou rce current and requires an extern al pull-up resistor to vref. 10 ramp this is the input for the sawtooth wa veform for the pwm comparator. using an rc from vref, a sawtooth waveform is created for use by the pwm. it is compared to the error amplifier output, ve rr, to create the pwm control signal. the ramp pin is shorted t o gnd at the termination of the pwm signal. 11 ovp input to detect an overvoltage (ov) condition on the outp ut. since the control variable is output current, a fault that re sults in an open circuit will cause excessive output voltage. the circuit hyst eresis is a switched current source that is active when the o v threshold is exceeded. 12 ac input to sense ac voltage presence and amplitude. a resistor divider from line and neutral/line and circuit ground is used to detect the ac voltage. 13 gnd signal and power ground connections for this device. due to high peak currents and high frequency operation, a low impedan ce layout is necessary. ground planes and short traces are highly recommended. 14 dhc an open drain fet used to load the input voltage to pre-load a triac-based dimmer so that adequate holding current is main tained.
isl1904 8 fn8286.1 september 20, 2012 15 pwmout the pwm gate drive output for led dimming. the output leve l is clamped to ~12v for vdd greater than 12v. pwmout has pul l- down capability when uvlo is active or when the ic is not biased. this output is used to drive the dimming fet in series with t he led string. the pwm operates at ~ 320hz. 16 out the gate drive output for the external power fet. out is capable of sourcing and sinking 1a @ vdd = 8v. the output level is clamped to ~12v for vdd greater than 12v. out has pull-down capability when uvlo is active or when the ic is not biased. pin descriptions (continued) pin # symbol description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl1904faz 1904 faz -40 to +125 16 ld qsop m16.15a ISL1904EVAL2Z evaluation board 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs comp liant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-free peak reflow temper atures that meet or exceed th e pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl1904 . for more information on msl please see tech brief tb363 . related products part number key differentiators isl1901 isolated and non-isolated single-stage flyback regulator. isl1902 isolated and non-isolated single-stage flyback regulator with inrush control and interface features for temperature and ambient light sensors. isl1903 non-isolated single-stage buck regu lator using switch current for regulation. isl1904 isolated single-stage flyback regulator with primary side current sense regulation. isl1907 non-isolated two-stage cascaded boost pfc + buck regu lator eliminates dependency on electrolytic capacitors. isl1908 isolated two-stage cascaded boost pfc + flyback regulator eliminates dependency on electrolytic capacitors.
isl1904 9 fn8286.1 september 20, 2012 absolute maximum ratings (n ote 4) thermal information supply voltage, vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +28.0v out, pwmout, dhc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to vdd signal pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v ref + 0.3v vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v to 6.0v peak out current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0a peak pwmout current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.0a esd classification human body model (per mil-std-883 method 3015.7) . . . . . . . . 2500v machine model (per eiaj ed-4701 method c-111) . . . . . . . . . . . . . 200v charged device model (per eos/es d ds5.3, 4/14/93). . . . . . . . 1000v latch up (per jesd-78b; class 1, level a) . . . . . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 16 ld qsop package (notes 5, 6) . . . . . . . 85 44 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . -55c to 150c maximum storage temperature range . . . . . . . . . . . . . . . -65c to 150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c supply voltage range (typical). . . . . . . . . . . . . . . . . . . . . . . . . 9 to 20 vdc caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. all voltages are with respect to gnd. 5. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. for jc , the ?case temp? location is taken at the package top center. electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram - isl1904? on page 2 and ?typical applicat ion schematics? beginning on page 3. v dd = 17v, r ramp = 54k , c ramp = 470pf, t a = -40c to +125c, typical values are at t a = +25c; boldface limits apply over the operating temperature range, -40c to +125c. parameter test conditions min (note 7) typ max (note 7) units supply voltage supply voltage -- 26 v start-up current, idd vdd = 5.0v - 100 200 a operating current, idd r load , c out = 0 - 6.0 7.8 ma uvlo start threshold 8.15 8.55 8.95 v uvlo stop threshold 6.80 7.10 7.50 v hysteresis -1.45- v reference voltage vref overall accuracy i vref = 0 - -10ma, 8v < v dd < 26v 5.30 5.40 5.50 v long term stability t a = 125c, 1000 hours (note 8) - 10 25 mv operational current (source) 8v < v dd < 26v - - -10 ma current limit vref = 5.00v, 8v < v dd < 26v -100 - -15 ma load capacitance (note 8) 0.1 - 3.3 f peak current sense (oc) current limit threshold v err = vref, ramp = 0v 570 595 616 mv iout amplifier gain v oc = 0.4v, 8v < v dd < 17v 3.83 4.00 4.18 v/v iout high level output voltage (voh) v iout @ 0a - v iout @ -100a, 8v < v dd < 26v -- 0.1 v iout low level output voltage (vol) v iout @ 100a, 8v < v dd < 26v - - 0.1 v leading edge blanking (leb) duration 70 120 146 ns oc to out delay + leb t a = 25c 110 170 200 ns input bias current v oc = 0.3v -1.0 - 1.0 a
isl1904 10 fn8286.1 september 20, 2012 ramp ramp sink current device impedance i ramp = 10 ma - - 20 ? ramp to pwm comparator offset t a = +25c 181 235 287 mv input bias current v ramp = 0.3v -1.0 - 1.0 a pulse width modulator pwm restart delay range 8v < v dd < 26v 0.2 - 2.0 s pwm restart cycle delay rdeladj = 20.0k, 8v < v dd < 26v 240 280 320 ns rdeladj = 210k, 8v < v dd < 26v 2.00 2.20 2.40 s maximum frequency clamp 8v < v dd < 26v, ramp = 2v, r ramp = 100 0.8 1.0 1.2 mhz minimum frequency clamp 8v < v dd < 26v, r ramp = 23k 20 25 31 khz minimum on time 8v < v dd < 26v, fb = 1v, ac = 2v, ramp = 0v 173 - 246 ns verr to pwm gain 8v < v dd < 26v - 0.200 - v/v ss to pwm gain 8v < v dd < 26v - 0.222 - v/v error amplifier input common mode (cm) range (note 8) 0 - 3.4 v gbwp (note 8) 1.9 --mhz verr vol i verr = 6ma, 8v < v dd < 26v - - 0.950 v verr voh i verr = 1ma (ext. pull-up) ss complete 3.90 4.00 4.20 v open loop gain (note 8) 70 --db offset voltage (vos) 8v < v dd < 26v -7.5 - 7.5 mv input bias current 8v < v dd < 26v -1.0 - 1.0 a current sense (cs+) zero current (crcm) detection threshold, falling 8v < v dd < 26v 6 - 30 mv input bias current 8v < v dd < 26v -1.0 - 1.0 a ac detector input bias current 8v < v dd < 26v -50 - 50 na detection threshold, falling 8v < v dd < 26v, ac peak = 100mv 18 32 51 mv detection threshold hysteresis 8v < v dd < 26v - 23 - mv input operating range 8v < v dd < 26v 0 - 4.00 v clamp voltage i acdetect = 1.0ma 6.8 7.2 7.6 v ea reference input range 8v < v dd < 26v 0 - 0.538 v electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram - isl1904? on page 2 and ?typical applicat ion schematics? beginning on page 3. v dd = 17v, r ramp = 54k , c ramp = 470pf, t a = -40c to +125c, typical values are at t a = +25c; boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter test conditions min (note 7) typ max (note 7) units
isl1904 11 fn8286.1 september 20, 2012 ea reference vs ac conduction angle i lpout = 0a, f = 120hz (rectified), 8v < v dd < 26v duty cycle ( ) = 98% 523 548 574 mv duty cycle ( ) = 75% 286 318 340 mv duty cycle ( ) = 50% 117 139 156 mv duty cycle ( ) = 25% 16 32 44 mv duty cycle ( ) = 10% 0 3 11 mv dhc low level output voltage (vol) v dhc = 10ma, vdd = 8v operating -- 600 mv turn-off delay after ac returns - 4.0 - s soft-start duration 289 389 483 ms reference soft-start initial step 11 27 43 mv offref input bias current -1.0 - 1.0 a operating range (excluding offset) 0 - 0.5 v threshold hysteresis 33 52 70 mv threshold offset 78 104 129 mv ac dropout disable delay -32-ms out high level output voltage (voh) v out @ 0ma - v out @ -100ma, vdd = 8v operating, ramp = 0v -0.35 1.2 v low level output voltage (vol) v out @ 100ma, vdd = 8v operating - 0.7 1.2 v rise time c load = 2.2nf, vdd = 8v, t 90% - t 10% -35 55 ns fall time c load = 2.2nf, vdd = 8v, t 10% - t 90% -25 40 ns output clamp voltage vdd = 20v, i load = -10a 10.5 12.0 13.4 v unbiased output voltage clamp vdd = 6v, i load = 5ma - - 1.9 v pwmout high level output voltage (voh) v out @ 0ma - v out @ -10ma, vdd = 8v operating -0.8 1.2 v low level output voltage (vol) v out @ 10ma, vdd = 8v operating -0.8 1.2 v rise time c load = 1nf, vdd = 8v operating, t 90% - t 10% -160 240 ns fall time c load = 1nf, vdd = 8v operating, t 10% - t 90% -160 240 ns output voltage clamp vdd = 20v, i load = -10a 10.5 12.0 13.4 v electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram - isl1904? on page 2 and ?typical applicat ion schematics? beginning on page 3. v dd = 17v, r ramp = 54k , c ramp = 470pf, t a = -40c to +125c, typical values are at t a = +25c; boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter test conditions min (note 7) typ max (note 7) units
isl1904 12 fn8286.1 september 20, 2012 unbiased output voltage clamp vdd = 6v, i load = 3ma - - 1.9 v frequency 291 320 349 hz maximum duty cycle refin = 0.5v - - 100 % minimum on-time refin = 0v - - 0.5 s ovp ovp threshold 1.46 1.50 1.54 v ovp hysteresis 10 20 27 a input bias current -1.0 - 1.0 a ovp clamp voltage i ovp = 1ma 5.4 - 7.0 v thermal protection thermal shutdown (note 8) 150 160 170 c hysteresis (note 8) - 25 - c notes: 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. 8. limits established by characteriza tion and are not production tested. electrical specifications recommended operating conditions unless otherwise noted. refer to ?functional block diagram - isl1904? on page 2 and ?typical applicat ion schematics? beginning on page 3. v dd = 17v, r ramp = 54k , c ramp = 470pf, t a = -40c to +125c, typical values are at t a = +25c; boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter test conditions min (note 7) typ max (note 7) units test waveforms and circuits figure 2. rise/fall time test circuit figure 3. rise/fall times 9 10 11 12 13 14 15 16 1 2 4 3 5 6 7 8 cs+ dhc offref pwmout vref out vdd oc ovp ac iout ramp gnd fb deladj verr isl1904 8v 1nf 470pf 5k 54k 0 to 1v 120hz out or pwmout t r t f 90% 10%
isl1904 13 fn8286.1 september 20, 2012 figure 4. oc +leb to out delay figure 5. ac mains to dhc timing test waveforms and circuits (continued) oc out oc threshold leading edge blanking oc propagation delay oc + leb to out delay ac mains dhc t delay t delay typical performance curves figure 6. reference voltage vs temperature figur e 7. ea reference vs ac signal duty cycle figure 8. delay vs deladj resistance figure 9. pwmout duty cycle vs ac signal duty cycle normalized v ref temperature (c) -40 -25 -10 5 20 35 50 65 80 95 110 125 0.996 0.997 0.998 0.999 1.000 1.001 0 102030405060708090100 0 100 200 300 400 500 ac conduction angle (% duty cycle 120hz) ea reference (mv) 0 25 50 75 100 125 150 175 200 225 0 0.5 1.0 1.5 2.0 2.5 delay resistance (k ?
isl1904 14 fn8286.1 september 20, 2012 functional description features the isl1904 led driver is an exce llent choice for low cost. ac mains powered single conversion led lighting applications. it provides active power factor co rrection (pfc) to achieve high power factor using critical conduction mode operation, and incorporates additional feat ures for compatibility with triac-based dimmers. furthermore, it uses primary side current sensing to regulate the output current, eliminating the need to cross the isolation boundary to close the feedback control loop. the isl1904 includes su pport for both pwm and dc current dimming of the output. oscillator the isl1904 uses a critical conduction mode (crcm) algorithm to control the switching behavior of the converter. the on-time of the primary power switch is held virtually constant by the low bandwidth control loop (in pfc applications). the off-time duration is determined by the time it takes the current or voltage to decay during the flyback period. when the mmf (magneto motive force) of the transformer decays to zero, the winding currents are zero and th e winding voltages collapse. either may be monitored and used to initiate the next switching cycle. the isl1904 monitors the crcm condition using the cs+ signal. it can be used to monitor either current or voltage. additionally, there is a user ad justable threshold, deladj, to delay the initiation of the next switching cycle to allow the drain-source voltage of the primar y switch to ring to a minimal. this allows quasi-zvs operation to reduce capacitive switching losses and improve efficiency. see ?quasi-resonant switching? on page 18. by its nature the converter operation is variable frequency. there are both minimum and maximum frequency clamps that limit the range of operation. the minimum frequency clamp prevents the converter from operating in the audible frequency range. the maximum frequency clamps prevents operating at very high frequencie s that may result in excessive losses. an individual switching period is the sum of the on-time, the off-time, and the restart delay duration. the on-time is determined by the control loop error voltage, verr, and the ramp signal. as its name impl ies, the ramp signal is a linearly increasing signal that starts at 0v and ramps to a maximum of verr/5 to 235mv. ramp requires an external resistor and capacitor connected to vref to form an rc charging network. if verr is at its maximum level of vref, the time required to charge ramp to ~850mv determines the maximum on-time of the converter. ramp is discharged every switching cycle when the on-time terminates. the off-time duration is determined by the design of the transformer, which depends on the required energy storage/transfer and the indu ctance of the windings. the transformer design also determ ines the maximum on-time that can be supported without saturation, so, in reality, the transformer design is critical to every aspect of determining the switching frequency range. the design methodology is similar to designing a discontinuous mode (dcm) flyback transformer except with the constraint that it must operate at the dcm/ccm boundary at maximum load and minimum input voltage. the difference is that the converter will always operate at the dcm/ccm boundary, whereas a dcm converter will be more discontinuous as the input voltage increases or the load decreases. in pfc applications, the design is further complicated by the input voltage waveform, a rectified sinewave. once the output power, po, the output current, io, the output voltage, vo, and the minimum input ac voltage are known, the transformer design can be started. from the minimum ac input voltage, the minimum dc equivalent (rms) input voltage must be determined. in pfc applications, the converter behaves as if the input voltage is an equivalent dc value due to the low control loop bandwidth. po determines the amount of energy that must be stored in the transformer on each switching cycle, but must be corrected for efficiency. this includes leakage inductance lo sses, winding losses, and all secondary side losses. this can be estimated as a portion of the total losses, or as is typically done, may be assigned all of the losses. a typical minimum operating frequency and maximum duty cycle must be selected. these ar e somewhat arbi trary in their selection, but do ultimately determine core size. the typical frequency is what occurs when the instantaneous rectified input ac voltage is exactly at the equivalent dc value. the frequency will be higher when the instantaneous input voltage is lower, and lower when the instantaneous input voltage is higher. however, the duty cycle at the equivalent dc input voltage determines the on-time for the entire ac half-cycle (pfc applications). the on-tim e is constant due to the low bandwidth control loop, but the off-time and duty cycle vary with the instantaneous input voltage since the peak switch current follows v = ldi/dt. the typical frequency may requir e adjustment once the initial calculations are complete to see if the operating frequency at the peak of the minimum ac in put voltage is acceptable. a rule of thumb is to select th e typical frequency 25% higher than the absolute lowest desired frequency that occurs when operating at the peak of the minimum input ac voltage. p in p o ------ - = w (eq. 1)
isl1904 15 fn8286.1 september 20, 2012 the first calculation required is to determine the required secondary inductance shown by equation 2. the turns ratio n sp is calculated next in equation 3. knowing the secondary inductance and the turns ratio, the primary inductance can be calculated by using equation 4. with this information, the lowest switching frequency, which occurs at maximum load and at the peak instantaneous input voltage at the minimum rms volt age, can be determined. by selecting the maximum duty cycle and a typical average frequency, the on-time is already determined by equation 5. the primary peak current at the end of the on-time is shown in equation 6: the peak secondary current is the peak primary current divided by the transformer turns ra tio shown in equation 7. and the off-time is shown in equation 8: the lowest switching frequency is the reciprocal of the sum of the on-time, the off-time, and the delay time is shown in equation 9. the delay time can be approximated if the equivalent drain-source capacitance (c oss ) of the primary switch is known. this value should also include any parasitic capacitance on the drain node. these parameters may not be known during the early stages of the design, but are typically on the order of 300ns to 500ns. if the lowest frequency does not meet the requirements, then iterative calculations may be required. the highest frequency is determ ined by the shortest on-time summed with t delay . the shortest on-time occurs at high line and minimum load, and occurs at or ne ar the ac zero crossing when the primary (and secondary) current is zero. the minimum non-zero on-time the isl1904 can produce is ~100ns, suggesting an operating frequency above 1mhz. in any event the maximum frequency clamp would limit the frequency to about 1mhz. once the primary and seco ndary inductances are known, the general formulae to calculat e the on-time and off-time at an equivalent dc input voltage are shown by equations 11 and 12: it is clear from the equations there is a linear relationship between load current and frequency. at some light load the frequency will be limited by the maximum frequency clamp. there is an inverse relationship between the input voltage and frequency and its effect is restri cted by the typical input voltage range. it should be noted, however, that the above equations assume full conduction angle of the ac mains. when conduction angle modulating dimmers are used to block a portion of each ac half-cycle, the switching currents remain essentially unchanged during the conduction portion of the ac half-cycle as the conduction angle is reduced. the conduction angle is reduced, not the amplitude of the waveform envelope. the result being the steady state frequency behavior will not vary much as the conduction angle is reduced. table 1. oscillator definitions v minrms = minimum rms input voltage v maxinrms = maximum rms input voltage = efficiency f min(avg) = typical frequency when v in (instantaneous) = minimum v in(rms) d max = maximum typical duty cycle desired dmin = minimum typical duty cycle t on(max) =f typ(avg) x d max t on on-time of the power fet controlled by out t off off-time duration required for crcm operation ls = secondary inductance lp = primary inductance nsp = transformer turns ratio, ns/np ip(peak) = peak primary current within a switching cycle t delay = user adjustable delay before the next switching cycle begins l s v o 1d max ? () ? () ?? ------------------------------------------- - = h (eq. 2) n sp v o 1d max ? () ? ?? ---------------------------------------------------- = (eq. 3) l p l s n sp 2 ------------- = h (eq. 4) t on d max f min avg () ------------------------ - = s (eq. 5) i p peak () ?? ---------------------------------------- = a (eq. 6) i s peak () () --------------------- - = a (eq. 7) t off l s i s peak () ? ------------------------------- - = s (eq. 8) f min 1 t on t off t delay ++ --------------------------------------------------- - = hz (eq. 9) t delay + () ? ? ----------------------------------------------------------------- (eq. 10) t off 2l s i o ?? ---------------------- - 1 l p n sp v o ?? ? -------------------------------- - + ?? ?? ?? ? = s (eq. 11) t on 2l p n sp i o ?? ? -------------------------------------- 1 l p n sp v o ?? ? -------------------------------- - + ?? ?? ?? ? = s (eq. 12)
isl1904 16 fn8286.1 september 20, 2012 soft-start operation soft-start is not user adjustable and is fixed at ~ 350ms. both the duty cycle and control loop reference have soft-start. this ensures a well behaved closed loop soft-start that results in virtually no overshoot. ac detection and reference generation the isl1904 creates a 0 to 0.5v reference for the led current control loop by directly measurin g the conduction angle of the ac input voltage. the reference chan ges only with conduction angle and is virtually unaffected by variation in either voltage amplitude or frequency. the isl1904 detects the conduc tion angle us ing a divider network across the ac line and connected to the ac pin, although it can also be located after the ac bridge rectifier. the advantage to sensing the ac voltage directly, rather than the rectified voltage, is that there is no error in detecting the ac zero crossing. if monitored after the ac rectifier bridge, the ac signal tracks the filter capacitor voltage, which may not discharge in phase with the ac voltage. this can lead to incorrect detection of the ac zero crossing. at light load, the filter capacitor may not fully discharge before the ac voltage begins to increase again, resulting in no detection of the ac zero crossing at all. the ac pin and has an input range of 0 to 4v. the peak of the input signal should range between 1 and 4 volts for uncompromised accuracy. the ac detection circuit measures both the duration of the ac conduction angle and the half-cycle duration. by comparing the two every half-cycle, the detection circuit creates a frequency independent reference that is updated each ac half-cycle. in the event of an ac outage, the ac mains frequency reference is lost. the isl1904 will force the reference to zero volts and reset the soft-start circuit appr oximately 35ms after the last ac zero crossing is detected. if ac is held above it detection threshold, the internal reference is forced to its maximum of 0.5v. ac may be directly coupled to a 90hz to 130hz pwm signal to generate a reference if dimming is desired without using an ac dimmer. primary current sensing the isl1904 is configured to regulate the output current by monitoring the primary switch current at the oc pin. the peak primary switch current is captured, processed, and output on iout as a pwm voltage signal mo dulated in proportion to the output current. the iout pwm frequency is the same as the converter switching frequency and its amplitude is equivalent to 4x the peak switch current during the previous on-time. it must be scaled and filtered before being input to the control loop at the fb pin. the required filter time constant depends on the compensated error amplifier bandwidth. the filter bandwidth must be greater than the contro l loop bandwidth, typically an order of magnitude greater, but it is generally not necessary to filter the iout pwm signal to a low ripple dc level. the compensated error amplifier, with its limited bandwidth, performs that function. figure 10. ac detection ac emi filter ac 9 10 11 12 13 14 15 16 gnd isl1904 figure 11. ac detection ac emi filter ac 9 10 11 12 13 14 15 16 gnd isl1904 figure 12. alternate ac detection ac emi filter ac 9 10 11 12 13 14 15 16 gnd isl1904
isl1904 17 fn8286.1 september 20, 2012 the oc pin also provides cycle-by-cycle overcurrent protection. the on-time is terminated if oc exceeds 0.6v nominal. there is ~120ns of leading edge blanking (leb) on oc to minimize or eliminate external filtering. dimming the isl1904 supports both pwm and dc current modulation dimming. in either case, the control loop determines the average current delivered to the load. the usual method of dimming an led string is to modulate the dc current through the string. dc current dimming is the lower cost method, but results in a no n-linear dimming characteristic due to the increasing efficacy of the leds as current is reduced. pwm dimming results in linear dimming behavior. for pwm dimming, an external fet, controlled by pwmout, is required to gate the drive signal to the switching fet. see ?typical application - dimmable dc input boost converter? on page 5 for an example. when pwmout is high, the main switching fet operates normally. when pwmout is low, the main switching fet gate signal is blocked and the converter is effectively off. this method is typically used wh en the led string is not ground referenced. another method uses an external fet to interrupt the led load current as shown in ?typical appl ication - isolated flyback with pwm dimming? on page 4. regardless of the dimming meth od used, the control loop determines the average current delivered to the load. it does not matter if the load current is dc or pulsed as long as the control loop bandwidth is sufficiently lower than the pulsed current frequency. the converter control loop and output capacitance operate to filter and average the converter output current independently of the actual load current waveform. the dimming pwm and control loop are linked together such that the pwm duty cycle tracks the main control loop reference setpoint. if the control loop is set for 50% load, for example, the dimming pwm duty cycle is set for 50%. the led current will be at 100% load for 50% of the time and 0% load for 50% of the time, which averages to the 50% average load setpoint. see figures 7 and 9 for a graphical representation of the relationship between the control loop reference and pwmout duty cycle. it should be noted that the pwmout duty cycle is not allowed to go to zero. control loop the control loop configuration is user adjustable with the selection of the external compensation components. for applications requiring power factor correction (pfc), a very low bandwidth integrator is used, typically 20hz or less. in other applications, the control loop bandwidth can be increased as required like any other externally compensated voltage mode pwm controller. referring to figure 13, the fet switching current flowing through rs, is applied to the oc pin of the isl1904. the peak signal is sampled, buffered, and output on iout as a pwm signal with a gain of four and a duty equal to the complement of the converter duty cycle (out). the voltage on iout, when averaged, is a scaled representation of the maximum steady state output current, io. where iout is the average value of iout. iout must be scaled such that at maximum output current io is equal to the maximum reference level (nominally 0.530v), while also limiting the maximum peak primary oc signal to less than the overcurrent threshold of 0.6v. where i ocl is the output current limit threshold, v oc is the current limit threshold, and rs is the current sensing resistor. once the value of rs is determined, equation 14 can be used to solve for the level of oc at any steady state current and input voltage when io is substituted for io cl . where v oc(ss) is the peak steady state value of oc corresponding for the specific operating conditions. as indicated previously, iout must be scaled properly prior to connection to the fb input. using equation 13, and the value of rs obtained from equation 14, the divider network to scale iout can be determined. the ea compensation depends on the bandwidth required for the application. for pfc applications the bw is necessarily limited to 20hz or less. for other applications, the bw may be increased as required up to about 1/5 of the lowest switching frequency allowed as described in ?oscillator? on page 14. for the low bw applications a type i compensation configuration is adequate. for higher bw applications, a type ii configuration may be required. figure 13 shows the ty pe i configuration. figures 13 and 14 show the type i and type ii configurations, respectively. figure 13. control loop configuration oc - iout processor + _ out oc iout verr fb ac reference generator r1 r2 c filter c fb r fb r s vref r pu xfmr isl1904 iout 8rs ? --------------- i o ? = v (eq. 13) r s v oc 22n sp i ocl 1 l p n sp v o ?? ? ---------------------------------- - + ?? ?? ?? ?? ? ------------------------------------------------------------------------------------------------- - = (eq. 14) v oc ss () ?? ? -------------------------------- - + ?? ?? ?? ?? ? ? = v (eq. 15)
isl1904 18 fn8286.1 september 20, 2012 ovp the isl1904 has independent overvoltage protection accessed through the ov pin. there is a nominal 20a switched current source used to create hysteresis. the current source is active only during an ov fault; otherwise, it is inactive and does not affect the node voltage. the magnitude of the hysteresis voltage is a function of the external resistor divider impedance. if the divider formed by r1 and r2 is sufficiently high impedance, r3 is not required, and the hysteresis is: if that does not result in the desired hysteresis then r3 is needed, and the hysteresis is: if the ov signal requires filtering, the filter capacitor, copt, should be placed as shown in figure 11. the current hysteresis provides great flexibility in setting the magnitude of the hysteresis voltage, but it is susceptible to noise due to its high impedance. if the hysteresis was implemented as a fixed voltage instead, the signal could be filtered with a small capacitor placed between the ov pin and signal ground. this technique does not work well when the hysteresis is a current source because a current source takes time to charge the filter capacitor. there is no instantaneous change in the threshold level rendering the current hysteresis ineffective. to remedy the situation, the filter capacitor must be separated from the ov pin by r3. the capacitor and r3 must be physically close to the ov pin. offref control the isl1904 provides the ability to disable the output based on the level of the control loop reference, set by the ac conduction angle on the ac pin. setting offref to a voltage between 0 and 0.6v determines the threshold vo ltage that disables the output. offref allows the designer to disable the output at a pre-determined load current to prevent undesirable behavior such as at light loading conditions when there may be insufficient current to maintain the holding current in a triac-based dimmer. se tting offref to less than 100mv disables this feature. offref has a nominal hysteresis of 50mv. quasi-resonant switching the isl1904 uses critical conduction mode pwm control algorithm. near zero voltage switching (zvs) or quasi-resonant valley switching, as it is sometimes referred to, can be achieved in the flyback topology by delayi ng the next switching cycle after the transformer current decays to zero (critical conduction mode). the delay allows the primary inductance and capacitance to oscillate, causing the switching fet drain-source voltage to ring down to a minimal. if the fet is turned on at this minimal, the capacitive switching loss (1/2 cv 2 ) is greatly reduced. the delay duration is set with a resistor from deladj to ground. figure 8 on page 13 shows the graphical relationship between the delay duration and the value of the deladj resistance. the relationship is linear for resistance values greater than ~ 20 k () + () -------------------------- - ? = v (eq. 16) ' v2010 6 ? r1 ?? = v (eq. 17) ' v2010 6 ? r1 r3 r1 r2 + () -------------------------- - ? + ?? ?? ?? = v (eq. 18) refin off () ? = v (eq. 19) refin on () ? = v (eq. 20) figure 16. quasi-resonan t near-zvs switching winding current fet d-s voltage
isl1904 19 fn8286.1 september 20, 2012 and can be estimated using equation 21. dhc (dimmer holding current) the dhc pin provides a method to pre-load a triac-based dimmer during the period of time when the ac is blocked, with overlap at each edge of the ac conduction period to ensure adequate holding current. dhc is an open drain fet used to control an external resistor to act as the load. dhc controls a resistor on the external high voltage start-up bias regulator. see ?typical applicat ion - dimmable isolated flyback? on page 3 for an example of its usage. note the series resistor and diode connecting vdd to the gate of the start-up bias fet. it is required to keep the device on when the ac voltage is near the zero-crossing. gate drive the isl1904 output is capable of sourcing and sinking up to 1a. the out high level is limited to the out clamp voltage or vdd, whichever is lower. thermal protection internal die over-temperature protection is provided. an integrated temperature sensor protects the device should the junction temperature exceed +160c. there is approximately +10c of hysteresis. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plane must be employed. vdd and vref should be bypassed directly to gnd with good high frequency capacitance. t delay 73.33 10.2 r deladj k () ? + (eq. 21)
isl1904 20 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8286.1 september 20, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl1904 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change august 27, 2012 fn8286.1 page 15: changed equation 6, from h to a. equation 7, from h to a. equation 8 page 17: changed equation 14 from v to ohms august 10, 2012 fn8286.0 initial release.
isl1904 21 fn8286.1 september 20, 2012 package outline drawing m16.15a 16 lead shrink small outlin e plastic package (qsop/ssop) 0.150? wide body rev 3, 8/12 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. package length does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. package width does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. terminal numbers are shown for reference only. 7. lead width does not include dambar protrusi on. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 8. controlling dimension: millimeter. index area 16 1 -b- 0.17(0.007) ca m bs -a- m -c- seating plane 0.10(0.004) x 45 0.25 0.010 gauge plane 3.99 3.81 6.20 5.84 4 0.25(0.010) b m m 0.89 0.41 0.41 0.25 5 8 0 1.55 1.40 0.249 0.191 4.98 4.80 3 1.73 1.55 0.249 0.102 0.31 0.20 7 0.635 bsc 5.59 4.06 7.11 0.38 0.635 detail ?x? side view 1 typical recommended land pattern top view side view 2

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